A Design Framework for Low Power Analog Filter Banks

We detail the design of multiresolution analog lter banks, linear models of cochlear function, with power dissipation being a prime engineering constraint. We propose that a reasonable goodness criterion is the information rate through the system, per Watt of power dissipated. Speech applications requiring lter banks with a wide frequency tuning range, from 20 Hz to 20 kHz, and low power consumption make the transconductance-C integrator in subthreshold CMOS the preferable integrator structure. As a way of example, the dynamic range of a lowpass lter is computed and subsequently used to design a lter bank that models faithfully cochlear micro-mechanics. The power consumption of the entire lter bank is computed from analytical expressions and is estimated as 355 nW, at 68 kbits/sec overall information rate at the output of the system.